There has been growing markets for high-frequency applications such as mm-wave radars; multi-Gb/s WLANs; 100 Gb/s Ethernet; and THz-imaging systems. The operation frequency of these applications ranges from 10 GHz to 1 THz, and high-speed bipolar transistors (such as InP DHBTs), especially using low-cost silicon-based IC platforms such as SiGe HBTs, are essential in realizing these applications.
There exists, however, a fundamental tradeoff between the device cutoff frequency (fT) and breakdown voltage (e.g., the collector-emitter breakdown voltage with the base open (BVCEO) and the collector-base breakdown voltage with the emitter open (BVCBO)). Normally higher fT can be achieved by increasing the doping level of the selectively implanted collector (SIC) region. In this way, the collector-base (CB) space charge region (SCR) shrinks, giving rise to lower carrier transit time. However, such method degrades the impact ionization within the CB SCR, causing higher multiplication factors (M−1) and lower breakdown voltages (BVCEO and BVCBO), which can potentially compromise both the RF output power and the signal-to-noise ratio of such systems. Such issue has already become critical in the highly-scaled SiGe HBTs, whose fT and maximum oscillation frequency (fmax) have well exceeded 100 GHz regime. Recent research bodes well for further scaling toward half-terahertz (500+GHz) performance at room temperature. In pursuit of higher BVCEO with little degradation in the ac performance, device engineers have had to sacrifice half of the dc current gain (β) for about 0.1 V increase in BVCEO.
What is needed, therefore, are improved semiconductor and transistor devices that include features such as improved avalanche breakdown behavior without adversely impacting device speed. Embodiments of the present invention are directed to such semiconductor and transistor devices.